Phase detecting circuit and pll circuit

ABSTRACT

A phase detecting circuit includes a latch circuit that switches, based on an OR signal and an NAND signal of two clock signals to be subjected to phase comparison, one of outputs used for generation of two pulse signals on an advance phase side and a delay phase side to a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and holds the output in the states.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.12/728,120, filed Mar. 19, 2010, which is based upon and claims thebenefit of priority from Japanese Patent Application No. 2010-023474,filed on Feb. 4, 2010, the entire contents of each of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a phase detecting circuit and aphase-locked loop (PLL) circuit.

2. Description of the Related Art

In a PLL circuit that generates a system clock signal synchronized witha reference clock signal, a phase detecting circuit generates, based ona phase difference of the system clock signal (a frequency-divided clocksignal) from the reference clock signal, two control pulse signals (anUP signal and a DOWN signal) given to a charge pump circuit.

The phase detecting circuit includes a first flip-flop circuit, a datainput to which is a power supply voltage and a clock input to which isthe frequency-divided clock signal, a second flip-flop circuit, a datainput to which is the power supply voltage and a clock input to which isthe reference clock signal, and an AND circuit that generates, based ontiming when an AND of data outputs of the first and second flip-flopcircuits holds, a reset signal simultaneously applied to reset terminalsof both the flip-flip circuits (see, for example, JP-A. 2005-51693(KOKAI) and JP-A. 2003-209464 (KOKAI)).

Consequently, with extinction timing of the reset signal set as the end,the UP signal is output from a data output terminal of the firstflip-flop circuit and the DOWN signal is output from a data outputterminal of the second flip-flop circuit. The reset signal is generatedwith pulse width set equal to time from the timing when the AND holdsuntil a delay time in the AND circuit elapses.

Specifically, one of the UP signal and the DOWN signal output from thetwo flip-flop circuits changes to a control pulse signal on an advancephase side, and pulse width on the advance phase side has time widthobtained by adding the pulse width of the reset signal to time widthcorresponding to a phase difference between both the clock signals. Theother of the UP signal and the DOWN signal changes to a control pulsesignal on a delay phase side and the pulse width on the delay phase sidehas the pulse width of the reset signal.

As a phase detecting function of the phase detecting circuit, the pulsewidth of the generated two control pulse signals is desirably pulsewidth corresponding to the phase signal between both the clock signalson the advance phase side, and is desirably pulse width as narrow aspossible on the delay phase side. Therefore, it is necessary to reducethe pulse width of the reset signal.

However, because of an operation characteristic of the flip-flopcircuits, the reset signal has minimum pulse width required for thereset signal. The pulse width of the reset signal cannot be reduced tobe smaller than the minimum pulse width. On the other hand, when thepulse width of the reset signal is set to the minimum pulse width,because of, for example, a fluctuation of threshold value due to use fora long time, in some case, an output reset signal is crushed and the twoflip-flop circuits cannot be reset. Delay time in the AND circuitfluctuates because of the influence of an operation condition,environmental temperature, and a manufacturing process. In theconfiguration of the phase detecting circuit explained above, it isnecessary to design the delay time in the AND circuit long to someextent such that pulse width that withstands various kinds offluctuation and is enough for the operation of the flip-flop circuitscan be obtained. Therefore, it is difficult to improve the function ofthe phase detecting circuit.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a phase detectingcircuit includes a latch circuit that switches, based on an OR signaland an AND signal of two clock signals to be subjected to phasecomparison, one of outputs used for generation of two pulse signals onan advance phase side and a delay phase side to a preparation operationstate for performing the phase comparison and a circuit operation stateafter the phase comparison, and holds the outputs in the states.

According to one aspect of the present invention, a PLL circuit includesa phase detecting circuit including a latch circuit that switches, basedon an OR signal and an AND signal of a reference clock signal to besubjected to phase comparison and a frequency-divided clock signalobtained by frequency-dividing a system clock signal, one of outputsused for generation of two pulse signals on an advance phase side and adelay phase side to a preparation operation state for performing thephase comparison and a circuit operation state after the phasecomparison, and holds the output in the states; a charge pump circuitthat supplies an electric current corresponding to pulse widths of thetwo pulse signals; a loop filter that converts the electric current fromthe charge pump circuit into a control voltage signal; and a voltagecontrol oscillation circuit that generates the system clock signalhaving a frequency corresponding to potential of the control voltagesignal.

According to one aspect of the present invention, a PLL circuit includesa first frequency dividing circuit that frequency-divides a referenceclock signal; a second frequency dividing circuit that frequency-dividesa frequency-divided clock signal obtained by frequency-dividing a systemclock signal; a phase detecting circuit including a latch circuit thatswitches, based on an OR signal and an AND signal of an output of thefirst frequency dividing circuit and an output of the second frequencydividing circuit to be subjected to phase comparison, one of outputsused for generation of two pulse signals on an advance phase side and adelay phase side to a preparation operation state for performing thephase comparison and a circuit operation state after the phasecomparison, and holds the output in the states; a charge pump circuitthat supplies an electric current corresponding to pulse widths of thetwo pulse signals; a loop filter that converts the electric current fromthe charge pump circuit into a control voltage signal; and a voltagecontrol oscillation circuit that generates the system clock signalhaving a frequency corresponding to potential of the control voltagesignal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the configuration of a PLLcircuit including a phase detecting circuit according to a firstembodiment of the present invention;

FIG. 2 is a circuit diagram illustrating the phase detecting circuitaccording to the embodiment;

FIG. 3 is a timing chart for explaining the operation of the phasedetecting circuit;

FIG. 4 is a characteristic chart for explaining a phase detectingfunction of the phase detecting circuit;

FIG. 5 is a block diagram illustrating the configuration of a PLLcircuit including a phase detecting circuit according to a secondembodiment of the present invention;

FIG. 6 is a waveform chart for explaining a relation between the phasedetecting function and the duty of the phase detecting circuit shown inFIG. 2;

FIG. 7 is a circuit diagram illustrating the phase detecting circuitshown in FIG. 5; and

FIG. 8 is a waveform chart for explaining the operation of a dutyadjusting circuit shown in FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of the present invention are explained in detailbelow with reference to the accompanying drawings. The present inventionis not limited by the embodiments.

FIG. 1 is a block diagram illustrating the configuration of a PLLcircuit including a phase detecting circuit according to a firstembodiment of the present invention. FIG. 2 is a circuit diagramillustrating the phase detecting circuit according to the presentinvention. FIG. 3 is a timing chart for explaining the operation of thephase detecting circuit. FIG. 4 is a characteristic chart for explaininga phase detecting function of the phase detecting circuit.

A PLL circuit 1 shown in FIG. 1 includes a phase detecting circuit 2, acharge pump circuit 3, a loop filter 4, a voltage control oscillator(VCO) 5, and a frequency dividing circuit 6.

The operation of the PLL circuit 1 is briefly explained. In theconfiguration explained above, the VCO 5 outputs a system clock signalFsys having a frequency corresponding to a control voltage input fromthe loop filter 4. The system clock signal Fsys is frequency-divided bythe frequency dividing circuit 6 and input to the phase detectingcircuit 2 as a frequency-divided clock signal VCLK. The phase detectingcircuit 2 compares the frequency-divided clock signal VCLK and areference clock signal FCLK input from the outside, and generates twocontrol pulse signals (an UP signal and a DOWN signal) based on a resultof the comparison (a phase difference). The charge pump circuit 3charges or discharges, based on the two control pulse signals, acapacitative element included in the loop filter 4, and causes the loopfilter 4 to output a predetermined control voltage to the VCO 5.According to the above operation, the system clock signal Fsys having apredetermined frequency synchronized with the reference clock signalFCLK is stably output from the VCO 5.

The phase detecting circuit 2 shown in FIG. 2 includes a latch circuit10 of a set/reset type, inverters 11 and 12 and a NAND circuit 13 thatconfigure a first input circuit, a NAND circuit 14 that configures asecond input circuit, an inverter circuit 15 and AND circuits 16 and 17that configure an output circuit, and buffers 18 and 19.

The latch circuit 10 includes NAND circuits 10 a and 10 b, inputterminals and output terminals of which are respectivelycross-connected. The reference clock signal FCLK is input to theinverter 11, one input terminal of the NAND circuit 14, and one inputterminal of the AND circuit 17 via the buffer 18. The frequency-dividedclock signal VCLK is input to the inverter 12, the other input terminalof the NAND circuit 14, and one input terminal of the AND circuit 16.

In the first input circuit, the reference clock signal FCLK is input tothe NAND circuit 13 via the inverter 11 and the frequency-divided clocksignal VCLK is input to the NAND circuit 13 via the inverter 12. Thefirst input circuit outputs the reference clock signal FCLK and thefrequency-divided clock signal VCLK to the other input terminal of theNAND circuit 10 a as a NAND signal. In other words, the first inputcircuit configures an OR circuit and outputs an OR signal of thereference clock signal FCLK and the frequency-divided clock signal VCLK.

In the second input circuit, the reference clock signal FCLK and thefrequency-divided clock signal VCLK are input to the NAND circuit 14.The second input circuit outputs the reference clock signal FCLK and thefrequency-divided clock signal VCLK to the other input terminal of theNAND circuit 10 b as a NAND signal.

In the output circuit, an output of the NAND circuit 10 b is input tothe other input terminals of the AND circuits 16 and 17 via the invertercircuit 15. The AND circuit 16 receives an output of the invertercircuit 15 and the frequency-divided clock signal VCLK and outputs theUP signal, which is one of the control pulse signals. The AND circuit 17receives the output of the inverter circuit 15 and the reference clocksignal FCLK and outputs the DOWN signal, which is the other of thecontrol pulse signals.

In FIG. 2, the other input terminal of the NAND circuit 10 a is used asa set terminal of the latch circuit 10 and the other input terminal ofthe NAND circuit 10 b is used as a reset terminal of the latch circuit10. The output of the NAND circuit 10 b corresponds to an output of thelatch circuit 10. When the relation of set and reset is reversed, anoutput of the NAND circuit 10 a is the output of the latch circuit 10.

The operation of the phase detecting circuit 2 is explained withreference to FIG. 3. In FIG. 3, operation performed when a phase of thereference clock FCLK is more advanced than a phase of thefrequency-divided clock signal VCLK (FCLK>VCLK) and operation performedwhen a phase of the reference clock FCLK is more delayed than a phase ofthe frequency-divided clock signal VCLK (FCLK<VCLK) are shown.

In the case of FCLK>VCLK, in a period until the reference clock signalFCLK rises, because the frequency-divided clock signal VCLK is also at alow level, an output of the NAND circuit 13 is at the low level and anoutput of the NAND circuit 14 is at a high level. Therefore, the latchcircuit 10 is in an initial state (a reset state) and an output of thelatch circuit 10 is at the low level. In this case, an output of theinverter circuit 15 is at the high level. However, because both thereference clock signal FCLK and the frequency-divided clock signal VCLKare at the low level, outputs of the AND circuits 16 and 17 remain atthe low level.

When the reference clock signal FCLK rises, the output of the NANDcircuit 13 changes to the high level. On the other hand, because theoutput of the NAND circuit 14 maintains the high level, the output ofthe latch circuit 10 maintains the low level latched earlier and theoutput of the inverter circuit 15 remains at the high level. Therefore,the DOWN signal, which is the output of the AND circuit 17, rises.

Thereafter, when the frequency-divided clock signal VCLK rises aftercertain time, the output of the NAND circuit 13 maintains the highlevel. However, the output of the NAND circuit 14 changes to the lowlevel. Therefore, the output of the latch circuit 10 changes to the highlevel. At this point, in FIG. 3, timing when the output of the NANDcircuit 14 changes to the low level and timing when the output of theNAND circuit 10 b changes to the high level are shown as substantiallythe same. However, because of delay time in transmission through thecircuits, the output of the NAND circuit 10 b is at the low level andthe output of the inverter circuit 15 is at the high level at the timingwhen the output of the NAND circuit 14 changes to the low level.Therefore, the UP signal, which is the output of the AND circuit 16rises at timing when the frequency-divided clock signal VCLK rises. Theoutput of the inverter circuit 15 changes to the low level after certaindelay time. The DOWN signal and the UP signal simultaneously fall.

In short, in the case of FCLK>VCLK, the pulse width of the UP signaldepends on “delay time” caused in a path leading from the NAND circuit14 to the inverter circuit 15 via the NAND circuit 10 b. The pulse widthof the DOWN signal is obtained by adding the “delay time” to time widthequivalent to a phase difference between the reference clock signal FCLKand the frequency-divided clock signal VCLK.

Thereafter, when the reference clock signal FCLK falls and thefrequency-divided clock signal VCLK falls, the output of the NANDcircuit 13 changes to the low level. The latch circuit 10 returns to theinitial state. In other words, the output of the latch circuit 10changes to the low level. The phase detecting circuit shifts to the nextcomparing operation.

In the case of FCLK<VCLK, a phase relation is opposite to that in thecase of FCLK>VCLK. Similarly, the UP signal and the DOWN signal aregenerated by adding the delay time caused in the path leading from theNAND circuit 14 to the inverter circuit 15 via the NAND circuit 10 bthereto.

As explained above, the phase detecting circuit 2 generates, with thecircuit configuration including the latch circuit, the two control pulsesignals (the UP signal and the DOWN signal) by adding delay time fromthe input of the two clock signals to the output of the latch circuitthereto. The “delay time” corresponds to the pulse width of a signal forsimultaneously resetting the two flip-flop circuits.

The phase detecting function of the phase detecting circuit 2 isexplained with reference to FIG. 4. In FIG. 4, a phase relation betweenthe reference clock signal FCLK and the frequency-divided clock signalVCLK is shown. On the abscissa, the right side indicates a phasedifference in the case of FCLK>VCLK and the left side indicates a phasedifference in the case of FCLK<VCLK. On the ordinate, the upper sideindicates the pulse width of the DOWN signal and the lower sideindicates the pulse width of the UP signal.

The pulse width of the DOWN signal changes along a straight line 21according to the phase difference in the case of FCLK>VCLK. The pulsewidth of the UP signal changes along a straight line 22 according to thephase difference in the case of FCLK<VCLK. An ideal state is indicatedby a straight line formed by the straight line 21 and the straight line22 passing the origin.

However, in the phase detecting circuit 2, the delay time appears asbiases 23 and 24 with respect to the straight lines 21 and 22 and makesthe straight lines 21 and 22 discontinuous. The same holds true in thephase detecting circuit including the two flip-flop circuits explainedabove. The pulse width of the reset signal appears as the biases 23 and24.

A first object of the present invention is to reduce the biases 23 and24 as much as possible, i.e., reduce the delay time to be added as muchas possible. A second object of the present invention is to make itpossible to surely reset the two flip-flop circuits in a lock state of aPLL circuit. The phase detecting circuit 2 according to this embodimentcan attain these objects.

The pulse width of the reset signal in the phase detecting circuitincluding the two flip-flop circuits needs to be certain width accordingto, for example, limitation on the circuit operation of the twoflip-flop circuits and a transistor characteristic of the AND circuitthat generates the reset signal. It is difficult to reduce the pulsewidth. On the other hand, the “delay time” in the phase detectingcircuit 2 depends on the path leading from the NAND circuit 14 to theinverter circuit 15 via the NAND circuit 10 b. The “delay time” can beeasily reduced to be shorter than the pulse width of the reset signaland the phase detecting function can be improved. As a result, in thePLL circuit 1 including the phase detecting circuit 2, frequencystabilization in the lock state can be realized. This makes it lesslikely that the PLL circuit 1 deviates from the lock state.

In the phase detecting circuit including the two flip-flop circuits, tosimultaneously set the two flip-flop circuits in the initial state, thereset signal generated from outputs of the two flip-flop circuits isused. However, when the pulse width of the reset signal is small, it islikely that the pulse width is crushed by a fluctuation of thresholdvalue or the like in a process of use for a long time in the AND circuitthat generates the reset signal. Therefore, in the lock state of the PLLcircuit, in some case, the two flip-flop circuits cannot be reset. Onthe other hand, in the phase detecting circuit 2 according to thisembodiment, when both the reference clock signal FCLK and thefrequency-divided clock signal VCLK are at the low level, the latchcircuit 10 is in the initial state. Therefore, the reset state can besecured as long as the PLL circuit is locked in a state in which boththe clock signals are in-phase.

An operation state of the latch circuit 10 in the operation process forphase comparison of the two clock signals explained above is asexplained below. Even if a first clock signal on the advance phase siderises, in a period until a second clock signal on the delay phase siderises, the latch circuit 10 is in the initial state (the reset state)and the output of the latch circuit 10 is set to the low level. In thisperiod, one control pulse signal simply rises and detection of a phasedifference is performed. When the second clock signal rises, the latchcircuit 10 changes the output to the high level after certain delaytime, maintains the high level until the second clock signal falls, andthen shifts to the initial state.

In short, a state in which the output of the latch circuit 10 is latchedto the low level can be referred to as a “preparation operation state”in which phase comparison is performed. On the other hand, a state inwhich the output of the latch circuit 10 is latched to the high levelcan be referred to as a “circuit operation state” after the phasecomparison.

According to the operation process in the phase comparison of the twoclock signals explained above, the latch circuit 10 changes to thepreparation operation state and the circuit operation state using an ORsignal and an AND signal of the reference clock signal FCLK and thefrequency-divided clock signal VCLK.

In other words, the phase detecting circuit 2 is not limited to theconfiguration shown in FIG. 2. The phase detecting circuit 2 only has tohave a configuration that changes to the preparation operation state andthe circuit operation state using the OR signal and the AND signal ofthe reference clock signal FCLK and the frequency-divided clock signalVCLK. The first input circuit and the second input circuit are also notlimited to the configuration shown in FIG. 2. The first input circuitand the second input circuit only have to have a configuration that cansupply the OR signal and the AND signal of the reference clock signalFCLK and the frequency-divided clock signal VCLK to the latch circuit10.

As explained above, according to the first embodiment, the delay timefor specifying the ends of the two pulse signals generated based on thephase difference between the two clock signals depends on the transitionof the output of the latch circuit. Therefore, the delay time can bereduced as much as possible and the improvement of the phase detectingfunction can be realized. As a result, in an incorporated PLL circuit,frequency stabilization in the lock state can be realized. This makes itless likely that the PLL circuit deviates from the lock state.

FIG. 5 is a block diagram illustrating a PLL circuit including a phasedetecting circuit according to a second embodiment of the presentinvention. FIG. 6 is a waveform chart for explaining a relation betweenthe phase detecting function and the duty of the phase detecting circuitshown in FIG. 2. FIG. 7 is a circuit diagram illustrating the phasedetecting circuit shown in FIG. 5. FIG. 8 is a waveform chart forexplaining the operation of a duty adjusting circuit shown in FIG. 7.

In a PLL circuit 26 according to the second embodiment, a phasedetecting circuit 27 is provided instead of the phase detecting circuit2 of the configuration shown in FIG. 1 and frequency dividing circuits28 and 29 are added to the configuration. Otherwise, the configurationof the PLL circuit 26 is the same as the configuration shown in FIG. 1.The frequency dividing circuit 28 gives a frequency-divided referenceclock signal FCLKx, which is obtained by frequency-dividing thereference clock signal FCLK, to the phase detecting circuit 27. Thefrequency dividing circuit 29 gives a re-frequency-divided clock signalVCLKx, which is obtained by further frequency-dividing thefrequency-divided clock signal VCLK, to the phase detecting circuit 27.

In FIG. 6, a phase relation between the reference clock signal FCLK andthe frequency-divided clock signal VCLK input to the phase detectingcircuit 2 near the lock state is shown. An anti-phase lock state 30 inwhich a phase is shifted 180 degrees is shown in the phase relation.

The phase detecting circuit 2 adopts a system for setting the latchcircuit 10 in the initial state when both the reference clock signalFCLK and the frequency-divided clock signal VCLK are at the low level.When the anti-phase lock state 30 shown in FIG. 6 occurs, the phasedetecting circuit 2 cannot set the latch circuit 10 in the initial stateand the PLL circuit is locked in an anti-phase state.

Therefore, the phase detecting circuit 27 shown in FIG. 7 includes dutyadjusting circuits 32 and 33 having a mechanism for delaying timing of arising edge of a clock signal and advancing timing of a falling edge ofthe clock signal. When the duty of the reference clock signal FCLK canbe controlled, this can be realized by providing the phase detectingcircuit 27 instead of the phase detecting circuit 2 in the PLL circuit 1shown in FIG. 1. On the other hand, when the duty of the reference clocksignal FCLK cannot be controlled, this can be realized by providing thephase detecting circuit 27 in the PLL circuit 26 (FIG. 5) to which thetwo frequency dividing circuits 28 and 29 are added.

In FIG. 7, the duty adjusting circuit 32 is interposed in a path leadingfrom the buffer 18, to which the frequency-divided reference clocksignal FCLKx is input, to the inverter 11. The duty adjusting circuit 33is interposed in a path leading from the buffer 19, to which there-frequency-divided clock signal VCLKx is input, to the inverter 12.

The duty adjusting circuit 32 includes serial inverters 32 a and 32 b asa minimum configuration. The duty adjusting circuit 33 includes serialinverters 33 a and 33 b as a minimum configuration.

The inverters 32 a and 32 b and the inverters 33 a and 33 b used forduty adjustment are CMOS inverters. In a CMOS inverter, a load drivingability of a PMOS transistor is inferior to that of an NMOS transistor.Therefore, usually, a ratio of channel widths of the PMOS transistor andthe NMOS transistor is designed to be about 2:1 such that timing of arising edge and timing of a falling edge are substantially the same.When the timing of the rising edge is delayed or the timing of thefalling edge is advanced, the channel width of the NMOS transistor isset to 1 to increase or reduce the channel width of the PMOS transistor.In the duty adjusting circuits 32 and 33 according to this embodiment, aratio of channel widths of PMOS transistors and NMOS transistors of theinverters 32 a and 33 a in the first stage is designed to be about 4:1.A ratio of channel widths of PMOS transistors and NMOS transistors ofthe inverters 32 b and 33 b in the next stage is designed to be about1:1.

The operation of the duty adjusting circuits 32 and 33 is explained withreference to FIG. 8. In FIG. 8, waveforms before and after dutyadjustment of the frequency-divided reference clock signal FCLKx and there-frequency-divided clock signal VCLKx are shown. Both the clocksignals before the duty adjustment is in a state in which the clocksignals are locked in phases opposite to each other.

In a duty adjustment period 35, timing of a rising edge of thefrequency-divided reference clock signal FCLKx input from the buffer 18is delayed by the duty adjusting circuit 32. Timing of a falling edge ofthe re-frequency-divided clock signal VCLKx input from the buffer 19 isadvanced by the duty adjusting circuit 33.

In a duty adjustment period 36, timing of a falling edge of thefrequency-divided reference clock signal FCLKx input from the buffer 18is advanced by the duty adjusting circuit 32. Timing of a rising edge ofthe re-frequency-divided clock signal VCLKx input from the buffer 19 isdelayed by the duty adjusting circuit 33.

Consequently, even if the frequency-divided reference clock signal FCLKxand the re-frequency-divided clock signal VCLKx are in an anti-phaselock state, when the clock signals are input to the inverters 11 and 12,timing when both the clock signals change to the low level is formed.Therefore, information indicating that both the clock signals change tothe low level can be given to the latch circuit 10 from the NAND circuit13 to set the latch circuit 10 in the initial state and surely preventboth the clock signals from changing to the anti-phase lock state.

As explained above, according to the second embodiment, a phasedetecting circuit that can surely reset, even if phases of two clocksignals are opposite to each other. As a result, in an incorporated PLLcircuit, it is possible to prevent phases of a reference clock signaland a system clock signal generated by a VCO from being locked in phasesopposite to each other.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A phase detecting circuit comprising: a latch circuit configured to switch, based on an OR signal and a NAND signal of two clock signals wherein the two clock signals are subjected to phase comparison, an output of the latch circuit configured to be used for generating two pulse signals on an advance phase side and a delay phase side, the output configured to switch between a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and configured to hold the output in the states; a first input circuit comprising first and second duty adjusting circuits configured to respectively adjust duties of the two clock signals, and output an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit; a second input circuit configured to output a NAND signal of the two clock signals to the other input terminal of the latch circuit; and an output circuit configured to output the two pulse signals based on the one output of the latch circuit and the two clock signals.
 2. The phase detecting circuit according to claim 1, wherein the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and the phase detecting circuit further comprises: first and second duty adjusting circuits configured to respectively adjust duties of the two clock signals; first and second inverters configured to respectively logically invert and output outputs corresponding thereto of the first and second duty adjusting circuits; a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit; a fourth NAND circuit configured to output a NAND signal of the two clock signals to the other input terminal of the second NAND circuit; a third inverter configured to logically invert and output an output of the second NAND circuit; and first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the two clock signals corresponding thereto.
 3. The phase detecting circuit according to claim 1, wherein the first and second duty adjusting circuits are configured to respectively adjust, with a serial circuit of two or more inverters, duties of the two clock signals, and output an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit.
 4. The phase detecting circuit according to claim 1, wherein the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and the phase detecting circuit further comprises: first and second duty adjusting circuits configured to respectively adjust, with serial inverters in two stages, duties of the two clock signals; first and second inverters configured to respectively logically invert and output outputs corresponding thereto of the first and second duty adjusting circuits; a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit; a fourth NAND circuit configured to output a NAND signal of the two clock signals to the other input terminal of the second NAND circuit; a third inverter configured to logically invert and output an output of the second NAND circuit; and first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the two clock signals corresponding thereto.
 5. A PLL circuit comprising: a phase detecting circuit comprising a latch circuit configured to switch, based on an OR signal and a NAND signal of a reference clock signal wherein the reference clock signal is subjected to phase comparison and a frequency-divided clock signal obtained by frequency-dividing a system clock signal, an output of the latch circuit configured to be used for generating two pulse signals on an advance phase side and a delay phase side, the output configured to switch between a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and configured to hold the output in the states; a charge pump circuit configured to supply an electric current corresponding to pulse widths of the two pulse signals; a loop filter configured to convert the electric current from the charge pump circuit into a control voltage signal; and a voltage control oscillation circuit configured to generate the system clock signal having a frequency corresponding to a potential of the control voltage signal, wherein the phase detecting circuit further comprises a first input circuit comprising first and second duty adjusting circuits configured to respectively adjust duties of the reference clock signal and the system clock signal, and output an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit; a second input circuit configured to output a NAND signal of the reference clock signal and the system clock signal to the other input terminal of the latch circuit; and an output circuit configured to output the two pulse signals based on the output of the latch circuit and the reference clock signal and the system clock signal.
 6. The PLL circuit according to claim 5, wherein in the phase detecting circuit, the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and the phase detecting circuit further comprises first and second duty adjusting circuits that respectively adjust duties of the reference clock signal and the system clock signal; first and second inverters configured to respectively logically invert and output outputs corresponding thereto of the first and second duty adjusting circuits; a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit; a fourth NAND circuit configured to output a NAND signal of the reference clock signal and the system clock signal to the other input terminal of the second NAND circuit; a third inverter configured to logically invert and output an output of the second NAND circuit; and first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the reference clock signal and the system clock signal corresponding thereto.
 7. The PLL circuit according to claim 5, wherein the phase detecting circuit comprises: the first and second duty adjusting circuits are configured to respectively adjust, with a serial circuit of two or more inverters, duties of the reference clock signal and the system clock signal, and output an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit.
 8. The PLL circuit according to claim 5, wherein in the phase detecting circuit, the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and the phase detecting circuit further comprises: first and second duty adjusting circuits configured to respectively adjust, with serial inverters in two stages, duties of the reference clock signal and the system clock signal; first and second inverters configured to respectively logically invert and output outputs corresponding thereto of the first and second duty adjusting circuits; a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit; a fourth NAND circuit configured to output a NAND signal of the reference clock signal and the system clock signal to the other input terminal of the second NAND circuit; a third inverter configured to logically invert and output an output of the second NAND circuit; and first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the reference clock signal and the system clock signal corresponding thereto.
 9. A PLL circuit comprising: a first frequency dividing circuit configured to frequency-divide a reference clock signal; a second frequency dividing circuit configured to frequency-divide a frequency-divided clock signal obtained by frequency-dividing a system clock signal; a phase detecting circuit comprising a latch circuit configured to switch, based on an OR signal and a NAND signal of an output of the first frequency dividing circuit and an output of the second frequency dividing circuit wherein the output of the first frequency dividing circuit and the output of the second frequency dividing circuit are subjected to phase comparison, an output of the phase detecting circuit configured to be used for generating two pulse signals on an advance phase side and a delay phase side, the output configured to switch between a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and configured to hold the output in the states; a charge pump circuit configured to supply an electric current corresponding to pulse widths of the two pulse signals; a loop filter configured to convert the electric current from the charge pump circuit into a control voltage signal; and a voltage control oscillation circuit configured to generate the system clock signal having a frequency corresponding to potential of the control voltage signal.
 10. The PLL circuit according to claim 9, wherein the phase detecting circuit comprises: a first input circuit comprises first and second duty adjusting circuits configured to respectively adjust outputs of the first and second frequency dividing circuits, and output an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit; a second input circuit configured to output a NAND signal of the outputs of the first and second frequency dividing circuits to the other input terminal of the latch circuit; and an output circuit configured to output the two pulse signals based on the one output of the latch circuit and the outputs of the first and second frequency dividing circuits.
 11. The PLL circuit according to claim 9, wherein in the phase detecting circuit, the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and the phase detecting circuit further comprises: first and second duty adjusting circuits configured to respectively adjust duties of the outputs of the first and second frequency dividing circuits; first and second inverters configured to respectively logically invert and output the outputs of the first and second frequency dividing circuits corresponding thereto; a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit; a fourth NAND circuit configured to output a NAND signal of the outputs of the first and second frequency dividing circuits to the other input terminal of the second NAND circuit; a third inverter configured to logically invert and output an output of the second NAND circuit; and first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the outputs of the first and second frequency dividing circuits corresponding thereto.
 12. The PLL circuit according to claim 9, wherein the phase detecting circuit further comprises: a first input circuit comprises first and second duty adjusting circuits configured to respectively adjust, with a series circuit of two or more inverters, duties of the outputs of the first and second frequency dividing circuits, and outputs an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit; a second input circuit configured to output a NAND signal of the outputs of the first and second frequency dividing circuits to the other input terminal of the latch circuit; and an output circuit configured to output the two pulse signals based on the one output of the latch circuit and the outputs of the first and second frequency dividing circuits.
 13. The PLL circuit according to claim 9, wherein in the phase detecting circuit, the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and the phase detecting circuit further comprises: first and second duty adjusting circuits configured to respectively adjust, with serial inverters in two stages, duties of the outputs of the first and second frequency dividing circuits; first and second inverters configured to respectively logically invert and output outputs corresponding thereto of the first and second duty adjusting circuits; a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit; a fourth NAND circuit configured to output a NAND signal of the outputs of the first and second frequency dividing circuits to the other input terminal of the second NAND circuit; a third inverter configured to logically invert and output an output of the second NAND circuit; and first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and output signals corresponding thereto of the first and second frequency dividing circuits. 